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figure 1. ads-118/118a functional block diagram ref dac register register 3-state output register 12 bit 1 (msb) 11 bit 2 10 bit 3 9 bit 4 8 bit 5 7 bit 6 6 bit 7 5 bit 9 4 bit 9 3 bit 10 2 bit 11 1 bit 12 (lsb) timing and control logic offset adjust 17 analog input 19 start convert 16 eoc 15 C + s/h buffer digital correction logic flash adc 1 flash adc 2 amp 21 +5v analog supply 20 C5v supply 18, 23 analog ground 13 +5v digital supply 14 digital ground 22, 24 no connect (ads-118a only) 17 enable (ads-118a only) block diagram datel's ads-118 and ads-118a are 12-bit, 5mhz, sampling a/d converters packaged in space-saving 24-pin ddips. the ads-118 offers an input range of 1v and has three-state outputs. the ads-118a has an input range of 1.25v and features direct adjustment of offset error. these functionally complete low-power devices (1.8 watts) contain an internal fast-settling sample/ hold ampli? er, a 12-bit subranging a/d converter, a precise voltage reference, timing/control logic, and error-correction circuitry. all timing and control logic operates from the rising edge of a single start convert pulse. digital input and output levels are ttl. models are available for use in either com- mercial (0 to +70c) or military (C55 to +125c) operating temperature ranges. applications include radar, transient signal analysis, process control, medical/graphic imaging, and fft spectrum analysis. product overview features 12-bit resolution 5mhz minimum sampling rate functionally complete small 24-pin ddip requires only 5v supplies low-power, 1.8 watts outstanding dynamic performance no missing codes over full military temperature range edge-triggered, no pipeline delay ideal for both time and frequency-domain applications * ads-118, pin 17 is enable ads-118a, pin 17 is offset adjust input/output connections pin function pin function 1 bit 12 (lsb) 24 no connection 2 bit 11 23 analog ground 3 bit 10 22 no connection 4 bit 9 21 +5v analog supply 5 bit 8 20 C5v supply 6 bit 7 19 analog input 7 bit 6 18 analog ground 8 bit 5 17* enable /offset adj. 9 bit 4 16 start convert 10 bit 3 15 eoc 11 bit 2 14 digital ground 12 bit 1 (msb) 13 +5v digital supply ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 1 of 8
physical/environmental parameters min. typ. max. units operating temp. range, case ads-118/118amc 0 +70 c ads-118/118amm, gm, 883 C55 +125 c thermal impedance jc 2 c/watt ca 23 c/watt storage temperature range C65 +150 c package type 24-pin, metal-sealed, ceramic ddip or smt weight 0.42 ounces (12 grams) absolute maximum ratings parameters limits units +5v supply (pins 13, 21) 0 to +6 volts C5v supply (pin 20) 0 to C6 volts digital input (pin 16, 17) C0.3 to +vdd +0.3 volts analog input (pin 19) 5 volts lead temperature (10 seconds) +300 c +25c 0 to +70c C55 to +125c analog input min. typ. max. min. typ. max. min. typ. max. units input voltage range, ads-118 ? 1 1 1 volts input resistance 475 500 475 500 475 500 input capacitance 6 15 6 15 6 15 pf digital input logic levels logic "1" +2.0 +2.0 +2.0 volts logic "0" +0.8 +0.8 +0.8 volts logic loading "1" +20 +20 +20 a logic loading "0" C20 C20 C20 a start convert positive pulse width ? 50 100 50 100 50 100 ns static performance resolution 12 12 12 bits integral nonlinearity (f in = 10khz) 0.75 1.0 1.5 lsb differential nonlinearity (f in = 10khz) 0.5 +0.75 0.5 0.95 0.75 +0.95 lsb full scale absolute accuracy 0.1 0.5 0.5 0.75 0.75 1.5 %fsr bipolar zero error (tech note 2) 0.1 0.5 0.5 0.85 0.85 2.0 %fsr bipolar offset error (tech note 2) 0.1 0.5 0.5 1.5 1.5 2.5 %fsr gain error (tech note 2) 0.1 0.5 0.5 1.0 1.0 2.5 % no missing codes (f in = 10khz) 12 12 12 bits dynamic performance peak harmonics (C0.5db) dc to 500khz C76 C71 C74 C70 C72 C66 db 500khz to 1mhz C75 C71 C74 C70 C70 C65 db 1mhz to 2.5mhz C69 C69 C73 C67 C66 C60 db total harmonic distortion (C0.5db) dc to 500khz C72 C68 C71 C67 C70 C65 db 500khz to 1mhz C71 C67 C70 C66 C67 C63 db 1mhz to 2.5mhz C70 C66 C69 C65 C66 C60 db signal-to-noise ratio (w/o distortion, C0.5db) dc to 500khz 67 69 66 69 64 67 db 500khz to 1mhz 66 69 65 68 63 66 db 1mhz to 2.5mhz 66 69 65 68 63 66 db signal-to-noise ratio ? (& distortion, C0.5db) dc to 500khz 65 68 64 67 62 66 db 500khz to 1mhz 65 68 64 67 61 65 db 1mhz to 2.5mhz 64 67 63 66 60 64 db noise 195 195 195 vrms two-tone intermodulation distortion (f in = 1mhz, 975khz, f s = 5mhz, C0.5db) C74 C74 C74 db input bandwidth (C3db) small signal (C20db input) 20 20 20 mhz large signal (C0.5db input) 10 10 10 mhz feedthrough rejection (f in = 2.5mhz) 80 80 80 db slew rate 400 400 400 v/s aperture delay time +10 +10 +10 ns aperture uncertainty 3 3 3 ps rms functional specifications (t a = +25c, v dd = 5v, 5mhz sampling rate, and a minimum 3 minute warmup ? unless otherwise speci? ed.) ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 2 of 8
errors can be reduced to zero using the adjustment circuitry shown in figures 2a and 2b. for operation without adjustment, tie pin 17 to analog ground. when using this circuitry, or any similar offset and gain-calibration hardware, make adjustments following warmup. to avoid interaction, always adjust offset before gain. 3. to enable the three-state outputs, connect enable (pin 17) to a logic "0" (low). to disable, connect pin 17 to logic "1" (high). the three-state outputs are permanently enabled in the ads-118a. 4. applying a start convert pulse while a conversion is in progress (eoc = logic "1") will initiate a new and inaccurate conversion cycle. +25c 0 to +70c C55 to +125c dynamic performance (cont.) min. typ. max. min. typ. max. min. typ. max. units s/h acquisition time ( to 0.001%fsr, 10v step) 85 90 85 90 85 90 ns overvoltage recovery time ? 200 200 200 ns a/d conversion rate 5 5 5 mhz digital outputs logic levels logic "1" +2.4 +2.4 +2.4 volts logic "0" +0.4 +0.4 +0.4 volts logic loading "1" C4 C4 C4 ma logic loading "0" +4 +4 +4 ma delay, falling edge of eoc to output data valid 20 20 20 mhz delay, falling edge of enable to output data valid 10 10 10 mhz output coding offset binary power requirements power supply ranges ? +5v supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.9 +5.0 +5.25 volts C5v supply C4.75 C5.0 C5.25 C4.75 C5.0 C5.25 C4.9 C5.0 C5.25 volts power supply currents +5v supply +205 +220 +205 +220 +205 +220 ma C5v supply C180 C205 C180 C205 C180 C205 ma power dissipation 1.8 2.1 1.8 2.1 1.8 2.1 watts power supply rejection 0.1 0.1 0.1 %fsr/%v footnotes: ? all power supplies should be on before applying a start convert pulse. all supplies and the clock (start convert pulses) must be present during warmup periods. the device must be continuously converting during this time. ? input voltage ranges for ads-118a is 1.25v ? a 100ns wide start convert pulse is used for all production testing. for applications requiring less than an 5mhz sampling rate, wider start convert pulses can be used. note: the device only requires the rising edge of a start convert pulse to operate. 1. obtaining fully speci? ed performance from the ads-118 requires careful attention to pc-card layout and power supply decoupling. the devices analog and digital ground systems are connected to each other internally. for optimal performance, tie all ground pins (14, 18, and 23) directly to a large analog ground plane beneath the package. bypass all power supplies to ground with 4.7f tantalum capacitors in parallel with 0.1f ceramic capacitors. locate the bypass capacitors as close to the unit as possible. 2. the ads-118 achieves its speci? ed accuracies without the need for external calibration. if required, the devices small initial offset and gain ? this is the time required before the a/d output data is valid once the analog input is back within the speci? ed range. ? the minimum supply voltages of +4.9v and C4.9v for v dd are required for C55c operation only. the minimum limits are +4.75v and C4.75v when operating at +125c (snr + distortion) C 1.76 + 20 log full scale amplitude actual input amplitude 6.02 ? effective bits is equal to: technical notes ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 3 of 8
to pin19 of ads-118 C15v signal input gain adjust 1.98k 50 +15v 2k 1.2m 20k C15v +15v zero/ offset adjust figure 2a. optional ads-118 external gain and offset adjust circuits signal input gain adjust 50 to pin19 of ads-118a potentiometer is at 25 during the device's factory trim procedure. 20k C15v (or C5v) +15v (or +5v) to pin17 of ads-118a zero/ offset adjust figure 2b. optional ads-118a gain and offset adjust circuits calibration procedure any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. to avoid interaction, offset must be ad- justed before gain. the ranges of adjustment for the circuits in figures 2a and 2b are guaranteed to compensate for the ads-118's initial accuracy errors and may not be able to compensate for additional system errors. a/d converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. this can be accomplished by connecting leds to the digital outputs and adjusting until certain led's "? icker" equally between on and off. other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. for the ads-118, offset adjusting is normally accomplished at the point where the msb is a 1 and all other output bits are 0s and the lsb just changes from a 0 to a 1. this digital output transition ideally occurs when the applied analog input is +?lsb (+244v for ads-118; +305v for ads-118a). gain adjusting is accomplished when all bits are 1s and the lsb just changes from a 1 to a 0. this transition ideally occurs when the ana- log input is at +full scale minus 1? lsb's (+0.99927v for ads-118; +1.249085v for ads-118a). zero/offset adjust procedure 1. apply a train of pulses to the start convert input (pin 16) so the con- verter is continuously converting. 2. apply +244v (ads-118) or +305v (ads-118a) to the analog input (pin 19). 3. adjust the offset potentiometer until the output bits are 1000 0000 00000 and the lsb ? ickers between 0 and 1. gain adjust procedure 1. apply +0.99927v (ads-118) or +1.249085v (ads-118a) to the analog input (pin 19). 2. adjust the gain potentiometer until all output bits are 1's and the lsb ? ickers between 1 and 0. 3. to con? rm proper operation of the device, vary the input signal to obtain the output coding listed in table 1. table 1. output coding for bipolar operation bipolar scale ads-118 input range (1v) output coding ads-118 input range (1.25v) offset msb binary lsb +fs C1 lsb +0.99951v 1111 1111 1111 +1.2494v +3/4 fs +0.75000v 1110 0000 0000 +0.9375v +1/2 fs +0.50000v 1100 0000 0000 +0.6250v 0 0.00000v 1000 0000 0000 0.0000v C1/2 fs C0.50000v 0100 0000 0000 C0.6250v C3/4 fs C0.75000v 0010 0000 0000 C0.9375v Cfs +1 lsb C0.99951v 0000 0000 0001 C1.2494v Cfs C1.00000v 0000 0000 0000 C1.2500v ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 4 of 8

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a9 a9 -3a9 -3a9 $,# # 0,#$ b% +% - + + figure 3. typical connection diagram figure 4. ads-118/118a timing diagram ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 5 of 8
electrically-insulating, thermally-conductive "pads" may be installed underneath the package. devices should be soldered to boards rather than socketed, and of course, minimal air ? ow over the surface can greatly help reduce the package temperature. in more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of datel's hs series heat sinks. see ordering information for the assigned part number. see page 1-183 of the datel data acquisition components catalog for more information on the hs series. request datel application note an8, "heat sinks for dip data converters", or contact datel directly, for additional information. thermal requirements all datel sampling a/d converters are fully characterized and speci? ed over operating temperature (case) ranges of 0 to +70c and C55 to +125c. all room temperature (t a = +25c) production testing is performed without the use of heat sinks or forced air cooling. thermal impedance ? gures for each device are listed in their respective speci? cation tables. these devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. the ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. figure 5. fft analysis of ads-118 0 C10 C20 C 3 0 C40 C50 C60 C70 C 8 0 C90 C100 C110 C120 C1 3 0 0 250 500 750 1 1.25 1.5 1.75 2 2.25 2.5 amplitude relative to full scale (db) khz khz khz mhz mhz mhz mhz mhz mhz mhz (f s = 5mhz, fin = 2.45mhz, vin = C0.5db, 4,096-point fft) frequency figure ads-118 istogram and differential nonlinearity digital output code +0.67 C0.47 0 4096 number of occurences 0 4096 digital output code dnl (lsb's) 0 ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters ?? datel ? 11 cabot boulevard, mans? eld, ma 02048-1151 usa ? tel: (508) 339-3000 ? www.datel.com ? e-mail: help@datel.com 31 mar 2011 ads-118.b03 page 6 of 8
figure 7. ads-118/118a evaluation board schematic (ads-b118)

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mechanical dimensions inches (mm) 24-pin ddip versions 0.200 max. (5.080) 0.235 max. (5.969) 0.600 0.010 (15.240) 0.80 max. (20.32) 0.100 typ. (2.540) 0.100 (2.540) 0.018 0.002 (0.457) 0.100 (2.540) 0.040 (1.016) 1.31 max. (33.27) 112 13 24 1.100 (27.940) 0.190 max. (4.826) 0.010 (0.254) +0.002 C0.001 seating plane 0.025 (0.635) dimension tolerances (unless otherwise indicated): 2 place decimal (.xx) 0.010 (0.254) 3 place decimal (.xxx) 0.005 (0.127) lead material: kovar alloy lead finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating pin 1 index 24-pin surface mount versions ads-118amc ads-118amm ads-118mc ADS-118MM 0. 8 0 max. (20. 3 2) 0.015 (0. 38 1) max. r a di us for a ny pin 1. 3 1 max. ( 33 .02) 0.100 typ. (2.540) 0.100 (2.540) 0.190 max. (4. 8 26) 0.040 (1.016) 0.020 typ. (0.50 8 ) 0.020 (0.50 8 ) 24 1 3 12 1 pin 1 index 0.1 3 0 typ. ( 3 . 3 02) dimension tolerances ( u nle ss otherwi s e indic a ted): 2 pl a ce decim a l (.xx) 0.010 (0.254) 3 pl a ce decim a l (.xxx) 0.005 (0.127) lead material: kov a r a lloy lead finish: 50 microinche s (minim u m) gold pl a ting over 100 microinche s (nomin a l) nickel pl a ting 0.060 typ. (1.524) 0.010 typ. (0.254) ordering information model number operating temp. range 24-pin package accessories ads-118mc 0 to +70c ddip ads-b118 evaluation board (without ads-118) ADS-118MM C55 to +125c ddip hs-24 heat sink for all ads-118 ddip models ads-118amc 0 to +70c smt ads-118amm C55 to +125c smt ads-118, ads-118a 12-bit, 5mhz, low-power sampling a/d converters . makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. the descriptions contained her ein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. speci? cations are subject to change without notice. www.datel.com ? e-mail: help@datel.com ?? datel 11 cabot boulevard, mans? eld, ma 02048-1151 usa itar and iso 9001/14001 registered 31 mar 2011 ads-118.b03 page 8 of 8

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